Linear Pluggable Optics: The AI Interconnect That Cuts Power Without Killing Serviceability

Linear Pluggable Optics: The AI Interconnect That Cuts Power Without Killing Serviceability

NEED TO KNOW

  • LPO is a pluggable optical module that drops the onboard DSP retimer and uses a linear analog chain (driver, modulator, photodiode, TIA, CTLE), so the host switch SerDes does equalization, CDR, and FEC.
  • Operationally, LPO keeps the pluggable service model CPO gives up: failed modules swap in seconds without taking the switch down; existing inventory, workflows, and field-test gear still work; standard QSFP-DD/OSFP cages allow multi-vendor mix-and-match; and ports can be populated as demand grows instead of paying for every optical channel up front. CPO still wins raw watts by shortening traces and removing more DSP tax, but LPO is the middle ground that cuts power and latency versus retimed optics without forcing a proprietary, chassis-level maintenance model.
  • Typical 800G LPO power is about 5.5–10 W versus 14–18 W for fully retimed modules; at 512 ports that can save ~500 W at the faceplate and ~1 kW including cooling, with latency falling from DSP nanoseconds to analog delay.
  • Reach stays short (about 500 m single-mode DR or tens of meters multimode SR). LPO is an intra-cluster / leaf-spine tool, not a campus replacement, and LRO remains the interoperability halfway house.
  • Supply is constrained by 200G InP EMLs and InP wafers more than by module assembly. Silicon photonics relocates the bottleneck onto CW lasers rather than eliminating III-V materials.
  • Volume modules concentrate at Chinese assemblers (Eoptolink, Innolight, CIG, Hisense, HG Tech); analog ICs at MACOM, Semtech, MaxLinear, Marvell, and Broadcom; lasers and substrates at Lumentum, Coherent, Sumitomo, JX, and China-exposed AXT capacity.

Linear pluggable optics (LPO) offer an immediate solution to the thermal limits of artificial intelligence racks. An LPO transceiver uses standard, hot-swappable QSFP-DD or OSFP module cages. However, it eliminates the digital signal processor (DSP) retimer inside the module. Instead, it assigns equalization, clock-and-data recovery (CDR), and forward error correction (FEC) back to the host switch SerDes /Broadcom/. What remains inside the module is a purely analog signal path. The transmit chain contains a linear driver and an optical modulator; the receive chain contains a photodiode, a high-linearity transimpedance amplifier (TIA), and a continuous-time linear equalizer (CTLE). Because it removes the power-hungry DSP, an 800G LPO module typically consumes 5.5–10 W rather than the 14–18 W required by a retimed module /LINK-PP/. Signal latency also falls from roughly 100 nanoseconds of DSP processing delay down to sub-nanosecond analog transit time. On a 64-port, 512-lane Tomahawk-class switch, this cuts approximately 500 W of module power directly at the board, which equates to nearly a full kilowatt of total power reduction once cooling fans and facility chillers are factored in.

The manufacturing challenge is preserving analog signal integrity at 56–112 Gbaud PAM4 /IEEE/. Linear drivers and TIAs, frequently fabricated in silicon-germanium (SiGe) BiCMOS processes, must limit total harmonic distortion (THD) to a few percent so that the four PAM4 voltage levels remain evenly spaced for the host equalizer. Production-grade LPO TIAs target input-referred noise below 2 µA rms, an optical-to-electrical bandwidth exceeding 40 GHz, and THD under 4.5% across several-hundred-millivolt output swings. Manufacturers co-package these analog dies alongside an optical engine: an electro-absorption modulated laser (EML) on indium phosphide (InP), a silicon-photonics integrated circuit driven by an external continuous-wave InP laser, or a short-reach vertical-cavity surface-emitting laser (VCSEL). Technicians attach fiber arrays and tune the assembly to match the host SerDes. The electrical interface relies on standards such as OIF CEI-224 linear (accommodating roughly 22 dB of die-to-die channel loss) and the LPO Multi-Source Agreement (MSA) 100G-per-lane single-mode specifications, with 200G-per-lane standards in progress. Without an internal DSP to mask signal degradation, production yield depends simultaneously on analog integrated circuit matching, laser linearity, and circuit board trace losses.

The primary obstacles regarding cost, scrap, and deployment time stem from multi-vendor interoperability and laser availability rather than module mechanical assembly. Removing the retimer removes the design margin that historically made plug-and-play modules straightforward. An LPO link works reliably only when engineers co-tune the switch ASIC, the printed circuit board traces, and the module’s analog equalizers. This interdependence explains why the industry spent 2024 and 2025 conducting interoperability plugfests, and why many operators still deploy Linear Receive Optics (LRO) which retains a transmit retimer while using a linear receiver as a practical transition step /IEEE/. Link distance remains short: typical limits are 500 meters for single-mode fiber (DR specifications) or tens of meters for multimode fiber (SR specifications). Consequently, LPO serves intra-cluster connections rather than long campus spans. The most constrained raw input is identical to retimed optics: 200G-per-lane InP EMLs and the 2- to 6-inch crystalline InP wafers on which they are grown. Module assemblers can remove the DSP to reduce wattage, but they cannot eliminate the laser. Silicon photonics simply transfers that physical requirement to high-power continuous-wave laser sources.

Primary end uses center on AI backend scale-out fabrics and dense leaf-spine switches inside hyperscale data centers. Industry forecasts project the LPO sector will reach low single-digit billions of dollars in 2025, expanding at a 20–27% compound annual growth rate into the early 2030s as 800G becomes standard and 1.6T linear designs arrive /C-Light/. The 800G tier already commands the largest share of high-speed forecasts because multi-rail GPU clusters multiply required optical transceiver ports much faster than they add physical racks. This bottleneck is not a finished-assembly shortage; market data show that optical component demand consistently outpaces supply, with high-speed 200G EMLs representing the tightest stock-keeping unit /EP/. North American hyperscalers buy the majority of these advanced optical modules, while Asian facilities assemble most of them. Additionally, one of the major operational advantages of LPOs in AI data centers is its retention of the standard pluggable form factor, which enables quick, hot-swappable field maintenance as opposed to alternatives like co-packaged optics (CPO).

The underlying industrial landscape is divided by geography and specialization. Chinese optical transceivers lead in finished volume: Eoptolink was first to demonstrate volume 800G LPO and 200G-per-lane hardware /Eoptolink/, while Innolight, CIG, Hisense Broadband, and HGTECH operate at comparable scale. In contrast, Western companies such as Coherent, Adtran, and specialized semiconductor firms largely supply the optical engines and analog silicon. Specialized linear driver and TIA production centers at MACOM, Semtech, MaxLinear, Marvell, and Broadcom. Switch host SerDes capable of driving unretimed linear optics are dominated by Broadcom Tomahawk and NVIDIA Spectrum ASIC platforms. Further upstream, InP crystal boule growth and wafer epitaxy are concentrated in Japan with Sumitomo Electric and JX Advanced Metals, alongside Chinese-supplied operations such as AXT; raw indium refining remains closely linked to Chinese zinc mining byproducts. This structure represents the primary geopolitical vulnerability: data centers in Virginia and Oregon rely on short-reach optical links built with Western-designed chips and lasers, but the high-precision packaging remains concentrated in manufacturing centers like Chengdu and Suzhou. LPO preserves the operational convenience of pluggable hardware while lowering the power footprint of the DSP, but it does not localize the underlying materials or cleanroom assembly.

Key Insights

What are the projected volume runs and install base requirements for 1.6T/800G linear pluggable optics in next-generation AI architectures like NVIDIA Vera Rubin NVL72 and AMD Helios clusters?

In next-generation rack-scale clusters such as NVIDIA’s Vera Rubin NVL72 and AMD Helios, scale-out network fabrics dictate an optical transceiver attach rate of roughly 2.5 to 5 units per accelerator, translating to an install base of 180 to 360 high-speed optical ports per 72-GPU rack across multi-tier rail-only and leaf-spine topologies. As these AI superclusters scale into hyperscale data center deployments through 2026 and 2027, annual industry demand for 800G and 1.6T interconnects is projected to cross tens of millions of units, driven primarily by transitions to 200G-per-lane SerDes. Linear pluggable optics (LPO and LRO) are positioned to capture an estimated 15% to 25% of this volume run—particularly in intra-rack and single-hop leaf-spine domains—by shaving roughly 500 to 1,000 watts of thermal overhead and sub-100-nanosecond DSP pipeline latency off each dense switch fabric.

What is the most critical process technology bottleneck in manufacturing LPO modules versus retimed DSP transceivers?

The primary manufacturing bottleneck for LPO is not pick-and-place surface-mount assembly or silicon foundry allocation, but the epitaxy yields and RF analog linearity of 200G-per-lane indium phosphide (InP) electro-absorption modulated lasers (EMLs) alongside SiGe BiCMOS analog front-ends. Because eliminating the DSP retimer removes downstream digital equalization and error masking, the link budget relies entirely on low-noise transimpedance amplifiers (sub-2 \muA_rms input-referred noise) and strictly linear laser drive (total harmonic distortion below 4.5% to preserve PAM4 level separation). Crucially, 200G-per-lane InP EML crystal growth remains constrained to 2- to 4-inch InP wafers that suffer from high defect densities and low substrate yields compared to mature silicon processes, creating an upstream material chokepoint that cannot be bypassed simply by adopting silicon photonics, which still demands high-power continuous-wave InP laser sources.

What are the unit economics, cyclicality, and margin defensibility of linear optics components under long-term supply agreements?

Stripping the advanced-node (3nm/5nm) DSP out of the bill of materials slashes raw component manufacturing costs by 20% to 30%, but margin defensibility shifts dramatically upstream to specialized analog IC vendors (e.g., MACOM, Semtech) and pure-play InP laser houses rather than module assemblers. Hyperscalers typically lock in multi-year Long-Term Supply Agreements (LTAs) for laser die allocations to hedge against cyclical capacity crunches, yielding 45% to 55%+ gross margins for linear TIA/driver and optoelectronic component suppliers with proprietary high-speed RF IP. In contrast, finished module assembly remains exposed to contract pricing erosion and geographic supply-chain friction, limiting white-box assembly gross margins to the low-20% range while making switch-and-module interoperability co-tuning the sole durable moat against commodity replacement.