Understanding Semiconductor Etch Machinery: Dry vs. Wet Processes in Advanced Chipmaking

Semiconductor etching machines carve microscopic patterns into silicon wafers to build AI microchips /sk hynix/. Foundries use two main etching methods: dry plasma etching and wet chemical etching. Dry plasma etching uses energized gas ions to cut straight vertical channels into silicon. Wet chemical etching uses liquid acid solutions to strip away unneeded chemical layers evenly.

Plasma etch, dominated by reactive ion etching and inductively coupled plasma systems, acts as the industry’s precision laser. By energizing gases into a plasma state, these tools blast ionized particles straight down into a wafer to achieve strict vertical, directional cuts. This capability is non-negotiable for the towering vertical architecture of modern chips, such as 3D NAND memory cells with depth-to-width ratios that exceed one hundred to one /Phys/, or the delicate vertical channels of Gate-All-Around nanosheets.

Selective wet chemical etching functions as a chemical process. Liquids, such as hydrofluoric acid for silicon dioxide or phosphoric acid for silicon nitride, react with unmasked material to remove it. Wet etching operates isotropically, dissolving material equally in all directions. Fabs use wet etching to clear large areas, strip entire films, or clean wafers between process steps. However, as feature sizes shrink below 10 nanometers, liquid surface tension can collapse tiny structures, making wet etching unsuitable for fine vertical patterns /ResearchGate/.

Yet, pushing chip design to two nanometers and beyond creates severe physical bottlenecks. As aspect ratios exceed 60:1 in 3D NAND memory and GAA nanosheets, ions struggle to reach the bottom of deep features without distorting sidewalls /Lam Research/. Aspect-ratio-dependent etching causes deeper holes to etch more slowly than shallow ones. Meanwhile, liquid surface tension in wet etching causes delicate nanostructures to bend and stick together. To overcome these limits, chipmakers are adopting cryogenic plasma etching, which cools wafers to sub-zero temperatures to protect sidewalls, alongside atomic layer etching (ALE) for removal of single atomic layers.

This technological revolution is fueling massive financial growth, driven by the explosive demand for advanced artificial intelligence hardware, high-bandwidth memory (HBM), and ultra-dense storage chips. The semiconductor etch equipment market, valued at ~$25 billion in 2025 is projected to expand to ~$40 billion by 2031 /Mordor Intelligence/. Momentum stems from the sharp rise in etch steps needed for sub-3 nm logic, the transition to gate-all-around transistors, the vertical scaling of 300-plus-layer NAND, and high-bandwidth memory stacks that demand through-silicon vias /EI/ with aspect ratios above 100:1. Memory applications already accounted for nearly 40% of 2025 revenue, while advanced packaging and HBM are expected to grow even faster, underscoring etch’s critical role in enabling denser, higher-performance AI silicon.

Despite this economic momentum, the industry sits on fragile geopolitical ground. Tool manufacturing is dominated by a tight oligopoly led by Lam Research, Tokyo Electron, and Applied Materials, alongside specialized players like SCREEN, Hitachi High-Tech, and emerging Chinese manufacturers like AMEC and NAURA. This concentration creates a delicate dual bottleneck for global chip production. On one side, advanced plasma tools remain tightly controlled by American and Japanese firms subject to strict export restrictions /CNBC/. On the other, the raw chemical supply chain remains heavily reliant on fluorspar /EI/, the key feedstock for hydrofluoric acid used in both wet and dry processes, over sixty percent of which is mined in China. Because extreme chip purity requirements make gas recycling economically difficult, the global buildout of next-generation AI hardware remains deeply vulnerable to both high-tech equipment controls and raw material trade friction.